1. Field of Invention
The present invention relates to a voltage reference circuit layout inside a multi-layered substrate. More particularly, the present invention relates to a multi-layered substrate having a reference signal trace in one of the non-signaling layers.
2. Description of Related Art
In most logic circuit chips or large-scale integrated circuits, a reference signal (V.sub.ref) is often required as a voltage reference standard for determining the voltage level of a logic signal and processing digital signals. More particularly, the logic circuit chip determines a signal at a high level when the signal has a voltage higher than the voltage of the reference signal. On the other hand, the signal is at a low level if the signal has a voltage lower than the voltage of the reference signal. Since accuracy of digital processing depends very much on the reference signal, a constant voltage level provided by the reference signal is always desired. To maintain a constant reference voltage level, coupling of voltage reference with other signals must be minimized. When there is voltage variation in the reference signal due to coupling with surrounding signals, the reference voltage no longer can serve as a standard for gauging the voltage level of other digital logic signals. Consequently, decision regarding logic level is likely to be in error and the entire system may break down. Hence, the maintenance of signal integrity through a reduction in the coupling with external signals is very important.
FIG. 1 is a schematic cross-sectional view of a conventional four-layered substrate. In general, a package substrate or a printed circuit board (PCB) has a four-layered structure. A four-layered substrate 100 is shown in FIG. 1. The four-layered substrate 100 includes a signal layer 104, a ground layer 108, a power layer 112 and another signal layer 116. An insulation layer 106 is formed between the signal layer 104 and the ground layer 108. Similarly, an insulation layer 110 is formed between the ground layer 108 and the power layer 112 and an insulation layer 114 is formed between the power layer 112 and the signal layer 116. In addition, a solder mask layer 102 and another solder mask layer 118 are formed over the signal layer 104 and the signal layer 116 respectively.
Circuits within the signal layer 104 and the signal layer 116 are used for signal inputs/outputs. Furthermore, the signal layers 104 and 116 may be electrically connected through plugs (not shown).
FIG. 2 is a schematic diagram showing a conventional reference signal circuit layout within a signal layer. As shown in FIG. 2, the reference signal circuit layout within the signal layer mainly comprises a reference signal trace and a plurality of signal traces. Using the signal layer 104 above the insulation layer 106 as an example, the reference signal circuit layout within the signal layer 104 mainly comprises a reference signal trace 104a and the signal traces 104b. The reference signal trace 104a and the signal traces 104b connect electrically with the signal layer 116 (shown in FIG. 1) through plugs 120. In general, signal transmitting within the reference signal trace 104a is frequently affected by signals transmitting within the nearby signal traces 104b due to coupling. Consequently, the voltage inside the reference signal trace 104a varies and a standard voltage reference level is hard to maintain.
FIG. 3 is a schematic diagram showing another conventional reference signal circuit layout within a signal layer. The reference signal circuit layout is very similar to the one in FIG. 2. One principle difference is that a double spacing is used between the signal traces 104b and the reference signal trace 104a so that coupling of the reference signal trace 104a with the signal traces 104b is lowered. However, the reference signal circuit layout in FIG. 3 still cannot completely eliminate interference due to electromagnetic field. Moreover, a compromise must be made between spatial layout limitation and acceptable degree of coupling.